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Espressif Systems /ESP32-P4 /LP_AON_CLKRST /LP_AONCLKRST_HPCPU_RESET_CTRL1

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Interpret as LP_AONCLKRST_HPCPU_RESET_CTRL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LP_AONCLKRST_HPCORE0_SW_STALL_CODE 0LP_AONCLKRST_HPCORE1_SW_STALL_CODE

Description

need_des

Fields

LP_AONCLKRST_HPCORE0_SW_STALL_CODE

HP core0 software stall when set to 8’h86
LP_AONCLKRST_HPCORE1_SW_STALL_CODE

HP core1 software stall when set to 8’h86

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data